1. Field of the Invention
The present invention relates to a method and to a circuit arrangement for expanding the addressing capacity of a central unit, in particular of a microprocessor, beyond the base address capacity defined by the address stock of an instruction counter.
2. Description of the Prior Art
As is well known in the art, the instruction counter of a central unit, such as a microprocessor, only has a limited address stock. With the addresses of this address stock individual program steps or instructions to perform defined operations can be offered. If addresses are required over and above this stock of addresses, one can provide a plurality of central units or microprocessors with corresponding instruction counters and split the functions to be performed between the two central units. This involves a circuit expense which is sometimes undesirable.